This invention relates to systems and methods for processing network packets.
A computer network (e.g., a local area network (LAN) or a wide area network (WAN)) consists of a group of two or more computers that are linked together. The computers (or processing systems) of a computer network typically transmit information over the network in the form of packets. A number of different packet-based protocols have been defined to enable interconnected network computers to communicate with each other. Generally, a network protocol requires each processing system connected to the network to check, process and route control information contained in each information packet.
A network processing system typically includes a network adapter that supports data communication between the processing system and the computer network. The network adapter may have either a host-based architecture or a packet-based architecture. With a host-based architecture, a network adapter transfers information packets by direct memory access (DMA) to host memory within the processing system as the information packets are received. With a packet-based architecture, on the other hand, a network adapter typically receives an entire information packet into adapter memory before transferring the information packet to host memory.
A number of different schemes have been proposed to reduce latency between the time a packet is received and the time the packet is processed. For example, U.S. Pat. No. 5,752,078 describes a network adapter that prepares a DMA transfer of an information packet to host memory before the entire information packet has been received. The ""078 purports that is packet processing approach reduces the user-perceived latency between the time an information packet is received by the network adapter and the time a user is notified that the information packet has been received. U.S. Pat. No. 5,948,079 describes a network peripheral device that transfers portions of a data packet to host memory in a non-sequential order to improve the efficiency with which the host system processes the data packet. International Patent Publication No. WO 00/10302 describes a programmable packet header processor that includes a plurality of parallel processing logic blocks for processing packet header information in accordance with one or more protocol handling operations. Still other packet processing schemes have been proposed.
The invention provides improved packet processing results by logically and physically separating packet header processing functions from packet data processing functions. In this way, the invention enables a network processing system to perform network handling operations and data processing operations substantially in parallel.
In one aspect, the invention features a network adapter for exchanging with a computer network information in the form of packets each including a packet header and packet data. The network adapter comprises a packet parser configured to parse an information packet into a packet header and packet data and to direct the packet header to a first memory address for protocol processing and to direct packet data to a second memory address for data processing.
Embodiments of the invention may include one or more of the following features.
The network adapter preferably includes an adapter header memory, wherein the first memory address corresponds to a location in the adapter header memory. The network adapter also preferably includes an adapter processor that is operable to interrogate packet header information stored in the adapter header memory in accordance with one or more network protocol handling operations. The adapter processor may be operable to program the packet parser with the first and second memory addresses for each network connection.
In one embodiment, the packet parser is configured to parse the packet header into two or more header components and to direct each header component to a respective memory address. In this embodiment, the network adapter preferably includes two or more adapter processors each of which is operable to process a respective one or more stored header components substantially in parallel.
The network adapter may be incorporated into a data processing system having a host memory and a host processor. In one embodiment, the second memory addressxe2x80x94to which packet data is directed for data processingxe2x80x94corresponds to a location in the host memory. The host processor preferably is operable to interrogate packet data stored in the host memory in accordance with one or more data processing operations.
In another embodiment, the network adapter includes an adapter data memory, wherein the second memory address corresponds to a location in the adapter data memory. In this embodiment, the network adapter preferably includes an adapter data processor that is operable to interrogate packet data stored in the adapter data memory in accordance with one or more data processing operations. The adapter data processor may be operable to perform encryption/decryption operations on packet data stored in the adapter data memory.
In another aspect, the invention features a processing system that includes a host memory, a host processor, and a network adapter for exchanging with a computer network information in the form of packets each including a packet header and packet data. The network adapter includes an adapter memory, an adapter processor, and a packet parser. The packet parser is configured to parse an information packet into a packet header and packet data and to direct the packet header to an adapter memory address for header processing by the adapter processor and to direct packet data to a host memory address for data processing by the host processor.
Another aspect of the invention features a packet processing method. In accordance with this method, an information packet is parsed into a packet header and packet data, and the packet header is directed to a first memory address for header processing and packet data is directed to a second memory address for data processing.